From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mail-a.sr.ht; dkim=pass header.d=maniero.me header.i=@maniero.me Received: from tiger.tulip.relay.mailchannels.net (tiger.tulip.relay.mailchannels.net [23.83.218.248]) by mail-a.sr.ht (Postfix) with ESMTPS id DFB412027B for <~johnnyrichard/olang-devel@lists.sr.ht>; Tue, 27 Feb 2024 23:50:58 +0000 (UTC) X-Sender-Id: hostingeremail|x-authuser|carlos@maniero.me Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 1F46836357A for <~johnnyrichard/olang-devel@lists.sr.ht>; Tue, 27 Feb 2024 23:50:57 +0000 (UTC) Received: from uk-fast-smtpout2.hostinger.io (unknown [127.0.0.6]) (Authenticated sender: hostingeremail) by relay.mailchannels.net (Postfix) with ESMTPA id 304A0363C91 for <~johnnyrichard/olang-devel@lists.sr.ht>; Tue, 27 Feb 2024 23:50:56 +0000 (UTC) ARC-Seal: i=1; s=arc-2022; d=mailchannels.net; t=1709077856; a=rsa-sha256; cv=none; b=8TAuAyyVDOlKFBrv0epTY2r29k7NMZPHT8Erl3hhgpmbWC6M/v56aVRyz41xRXvWH8ppcZ T6mpgoJ99K2DYqrsA/q88G9FYCB1/cvZLKX7iempRe0EOFNz7H6xq6FiD2sxMX7SIMCnLM emmORcjjTQadCLT5InLoIYiAPXZNA16zFi/oezeAeUpiTe3VIEKdk3hk/uZaPFyz7P3mRy 8NEqsN/Tv84uII+nmnC7D7I7jHGkie8I9Dwk3eX/vjR1ft0wfR6jQa0ih7klXN6/y2Aac8 gZ1p+bHt/WRG3Cuai8xfniVweD8KxJxoFBi0DqizgaLQkaVnxJT4YwAUbecQfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=mailchannels.net; s=arc-2022; t=1709077856; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=2WsC5QEdp1fVQLH2OnsWvdXpr7+17MZITSquvfI9aDE=; b=90V+SkckwxTLOTlh0kde+NayypV9Cf9I46a2ufJ+Crz/DEgtBc8gBG22xe/+xfqOT67dgn KXIOJMEJTQCFam/4CJdRdQnBAin49OicdrJQzwJYBeri70uwjKGQ90sEALlPhLvhIAUb8J 1qx6WV8ChpBlg6DqzFgRrHc250i3gPiA2uMw4VIBi2V1bvY3EewfThxjL1XkMXOwWSZUP5 +7MLClUec2i1mUqDwfqGoAqeT1Q+Z+58nMcVcwP7JhlJKE8AELyYAw80k6bG95SWYG7ZQG GkYqmNHR3fjQzcsUOeKhthrRUp1Gebh+k9I0SSpiskzvSDfzqKPGEV/QJmWtJg== ARC-Authentication-Results: i=1; rspamd-55b4bfd7cb-jlpd4; auth=pass smtp.auth=hostingeremail smtp.mailfrom=carlos@maniero.me X-Sender-Id: hostingeremail|x-authuser|carlos@maniero.me X-MC-Relay: Neutral X-MailChannels-SenderId: hostingeremail|x-authuser|carlos@maniero.me X-MailChannels-Auth-Id: hostingeremail X-Abiding-Robust: 30302d73021816fd_1709077856895_710259704 X-MC-Loop-Signature: 1709077856894:661893313 X-MC-Ingress-Time: 1709077856894 Received: from uk-fast-smtpout2.hostinger.io (uk-fast-smtpout2.hostinger.io [31.220.23.36]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384) by 100.101.14.245 (trex/6.9.2); Tue, 27 Feb 2024 23:50:56 +0000 Mime-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maniero.me; s=hostingermail1; t=1709077854; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2WsC5QEdp1fVQLH2OnsWvdXpr7+17MZITSquvfI9aDE=; b=ps4LgSbBdAl/+Xjmu7DvzskHMqFC7oKAv4i2QSsIF22kYX9tJnVF10Dr+T/vFz9rNBw9Sh 3pKiBvMX8bZJqPaLJfdw9+QTzj2DrPOj0zV8wbJZH1UQHGvL6l8uU33e073ZCV8NMzxOjQ N7Gpm5ucH+i3jfbWoG7LKkIaNoKLrT2IhQhWLUZSB+QbR0PMbRKI4vxJfspTM5h63iw/KQ vXTZ2SlzF6KwAu63e+QmdFl6uwimCsxResPMUElXhkQak2Y5sOY7HCw7gZNFqyKyNO2XV7 l1LKANnsPJK42Im99D3nt0ytgYp7Sm2ZDCtpOiK4rjIrCCiKclH84Etr+3oNHw== Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 27 Feb 2024 20:50:48 -0300 Message-Id: Subject: Re: [PATCH olang] arena: optimization: make arena 8 bits aligned From: "Carlos Maniero" To: "Carlos Maniero" , <~johnnyrichard/olang-devel@lists.sr.ht> X-Mailer: aerc 0.15.2-211-g37d5fc691aff References: <20240221055237.3231555-1-carlos@maniero.me> In-Reply-To: <20240221055237.3231555-1-carlos@maniero.me> X-CM-Analysis: v=2.4 cv=WakKaVhX c=1 sm=1 tr=0 ts=65de755d a=5+VMC1FZ3J4mVPAKpPmAqg==:117 a=5+VMC1FZ3J4mVPAKpPmAqg==:17 a=IkcTkHD0fZMA:10 a=MKtGQD3n3ToA:10 a=1oJP67jkp3AA:10 a=BXDaF_L80NYA:10 a=QyXUC8HyAAAA:8 a=rZMiO_E4RqOlQ4wNTEUA:9 a=QEXdDO2ut3YA:10 X-CM-Envelope: MS4xfK2WKd7E/LEebv2eSFBzJNDNr3g1SbPrrr9csx8bYVP7CjxLJpkLembqky5ZxKrySkXKjsWxxcpdKUuHGCRgcTsLKWjYoKnSpYmCiq7ZbRUpPe6EXxlx Uyg5ualpvGKL1jRprA0u24tPhiya2Yh1RsJm6ubSHXlsTukoIkVcgPJ2Il6c1G0jx6j6JGBayn4HffCBOOQHCJAqJt+RIZP1ulqb/DjGsDBHA3MuHE3NGqLI X-AuthUser: carlos@maniero.me X-TUID: EEBEBHfcUqQQ There is a lot that I learned since I started this patch. First of all, this patch has a bug. > + arena->offset +=3D size + (size % 8); Let's say the offset is zero and the size is one, we would expect the new offset to be 8 after the *arena_alloc*, but this code was producing 1 as the new offset. Furthermore, 8 is not the right memory alignment for x86_64 architectures according Intel's manual: > 4.1.1 Alignment of Words, Doublewords, Quadwords, and Double Quadwords >=20 > Words, doublewords, and quadwords do not need to be aligned in memory on > natural boundaries. The natural boundaries for words, doublewords, and > quadwords are even-numbered addresses, addresses evenly divisible by > four, and addresses evenly divisible by eight, respectively. However, to > improve the performance of programs, data structures (especially stacks) > should be aligned on natural boundaries whenever possible. The reason > for this is that the processor requires two memory accesses to make an > unaligned memory access; aligned accesses require only one memory > access. A word or doubleword operand that crosses a 4-byte boundary or a > quadword operand that crosses an 8-byte boundary is considered unaligned > and requires two separate memory bus cycles for access. >=20 > Some instructions that operate on double quadwords require memory > operands to be aligned on a natural boundary. These instructions > generate a general-protection exception (#GP) if an unaligned operand is > specified. A natural boundary for a double quadword is any address > evenly divisible by 16. Other instructions that operate on double > quadwords permit unaligned access (without generating a > general-protection exception). However, additional memory bus cycles > are required to access unaligned data from memory. https://cdrdv2.intel.com/v1/dl/getContent/671200 So ideally we must align arena on 16 bits. I'll send a v3 with theses two things fixed.